digital multi-phase buck controller chl8102/03/04/13 august 28, 2013 | final | v1.09 1 features ? dual output 2/3/4+1-phase pwm controller (chl8102/03/04) and single output 3-phase pwm controller (chl8113) ? easiest layout and fewest pins in the industry ? footprint compatible with chl8325a/b (chl8103/4) ? fully supports intel? vr12 (chl8103/04/13) and amd? svi with dual ocp & programmable addressing (chl8103/04) ? i2c interface for configuration & telemetry ? pin programmable i2c address (chl8103/04/13) ? overclocking support with i2c voltage override and vmax setting ? flexible i2c bus security features ? i2c security enable pin (chl8103/04/13) ? independent loop switching frequencies from 200khz to 1.2mhz per phase ? ir efficiency shaping with dynamic phase control (dpc) ? 1-phase & active diode emulation modes for light load efficiency ? ir adaptive transient algorithm (ata) on both loops minimizes output bulk capacitors and system cost ? per-loop fault protection: ovp, uvp, ocp ? thermal protection (otp) and vrhot# flag (chl8103/04/13) ? multiple time programmable (mtp) memory for custom configuration ? compatible with ir atl and 3.3v tri-state drivers ? 3.3v +10%/-15% supply voltage; 0oc to 85oc operation ? pb -free, rohs, qfn packages applications ? intel? vr12 & amd? svi based systems ? high performance desktops cpu vrs ? value servers cpu & ddr memory vrs description the chl8102/03/04 are dual-loop, digital multi-phase buck controllers designed for cpu voltage regulation. the chl8113 is a single-loop, digital multiphase buck controller ideal for server ddr memory voltage regulation. they are fully compliant with the intel? vr12 and amd? svi (chl8103/04) specifications. the chl8102/03/04/13 includes ir efficiency shaping technology to deliver exceptional efficiency at minimum cost across the entire load range. ir dynamic phase control adds/drops active phases based upon load current and can be configured to enter 1-phase operation and diode emulation mode automatically or by command. ir s uiue adaptie tasiet algoith ata, ased o proprietary non-linear digital pwm algorithms, minimizes output bulk capacitors and multiple time programmable (mtp) storage saves pins and enables a small package size. device configuration and fault parameters are easily defined using the ir digital power design center (dpdc ) gui and stored in on-chip mtp. the chl8102/03/04/13 provides extensive ovp, uvp, ocp and otp fault protection and the chl8103/04/13 includes thermistor based temperature sensing with vrhot signal. the chl8102/03/04/13 includes numerous features like register diagnostics for fast design cycles and platform differentiation, truly simplifying vrd design and enabling fastest time- to - aket ttm ith set -and- foget methodology. pin diagram pwm_l2 vrtn rcsm isen 3 vsen pwm4 (chl8104)/ nc (chl8103) vr_ready 1 / pwrgd 2 irtn 3 rcsp tsen1 pwm3 v18a rres vcc isen 2 isen 1 irtn 1 irtn 2 pwm2 pwm1 rcsm_l2 rcsp_l2 vpgm2 vinsen vrtn_l2 vsen_l2 1 2 7 8 5 6 3 4 10 9 30 29 24 23 26 25 28 27 21 22 41 gnd chl8103/4 40 pin 6x6 qfn top view 12 16 14 19 13 17 15 20 18 11 39 35 37 32 38 34 36 31 33 40 vr_ready_l2 1 / pwrok 2 1 intel mode 2 amd mode sv_alert 1 /nc 2 sv_clk 1 /svc 2 sv_dat 1 /svd 2 vr_hot# enable addr/prot/en_l2 smb_dat smb_clk tsen2 irtn4 (chl8104)/ nc (chl8103) isen4 (chl8104)/ nc (chl8103) irtn_l2 isen_l2 figure 1: chl8103/04 package top view downloaded from: http:///
digital multi-phase buck controller chl8102/03/04/13 august 28, 2013 | final | v1.09 2 pin diagram enlarged pwm_l2 vrtn rcsm isen 3 vsen pwm4 (chl8104)/ nc (chl8103) vr_ready 1 / pwrgd 2 irtn 3 rcsp tsen1 pwm3 v18a rres vcc isen 2 isen 1 irtn 1 irtn 2 pwm2 pwm1 rcsm_l2 rcsp_l2 vpgm2 vinsen vrtn_l2 vsen_l2 1 2 7 8 5 6 3 4 10 9 30 29 24 23 26 25 28 27 21 22 41 gnd chl8103/4 40 pin 6x6 qfn top view 12 16 14 19 13 17 15 20 18 11 39 35 37 32 38 34 36 31 33 40 vr_ready_l2 1 / pwrok 2 1 intel mode 2 amd mode sv_alert 1 /nc 2 sv_clk 1 /svc 2 sv_dat 1 /svd 2 vr_hot# enable addr/prot/en_l2 smb_dat smb_clk tsen2 irtn4 (chl8104)/ nc (chl8103) isen4 (chl8104)/ nc (chl8103) irtn_l2 isen_l2 downloaded from: http:///
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